The present disclosure relates to image sensors and imaging systems, and more particularly to a ramp-signal generator circuit that outputs a reference signal to a single slope (or integrating- or counter-type) analog-to-digital converter (hereinafter referred to as an ADC) included in an image sensor or an imaging device.
Image sensors each of which performs column parallel analog-to-digital (AD) conversion with an ADC provided in each column of a pixel array of the image sensor such that pixel output signals from a single row of the pixel array are subjected to AD conversion at a time in a horizontal scanning period, have been developed and put into practical use. In this column parallel AD conversion, a single-slope ADC whose circuit scale is relatively small is typically employed because of a limited area of each column determined depending on the pixel pitch (see, for example, Japanese Patent Publication No. 2006-340044). In the single-slope ADC, a ramp signal correlated with a count value of a counter is input as a reference signal to a comparator of the ADC, and based on a count value obtained when this reference signal coincides with an analog input signal (a pixel output signal), an AD conversion result is output as a digital signal.
FIG. 12 is a block diagram illustrating an example configuration of a conventional image sensor.
A column parallel ADC (a single-slope ADC) 620 includes comparators 660 (661-66p) (where p is a natural number) and counters 670 (671-67p). The column parallel ADC 620 compares, in the comparators 660, a reference signal Vr from a ramp-signal generator circuit 630 with pixel signals Vs1-Vsp from a pixel array 610, and based on counting results of comparison results Vc1-Vcp obtained by the counters 670 (671-67p), outputs an AD conversion result (a digital signal).
The column parallel ADC 620 included in the image sensor performs AD conversion through a procedure called digital correlated double sampling (CDS). In the digital CDS, two AD conversion processes, i.e., an AD conversion process on reset levels of the pixel signals Vs1-Vsp and an AD conversion process on a signal level, are performed, and the difference between these AD conversion processes is used as an AD conversion result on the Vs1-Vsp so as to reduce fixed pattern noise due to characteristic variations among pixels of the pixel array 610 and the comparators 660.
Referring to a timing chart of FIG. 13, operation of the digital CDS will be specifically described.
First, in a period from time T30 to time T31, the pixel array 610 outputs a reset level voltage V1 as a pixel signal Vsx (where x=1−p). The reference signal Vr from the ramp-signal generator circuit 630 is set at an initial voltage VI that has been previously set by the control circuit 640. In this state, the control circuit 640 sets a reset signal CRST at “L” and resets the comparators 660. Specifically, a comparator 66x (where x=1−p) includes a differential amplifier having input capacitances 3a and 3b and an inverter (INV) amplifier 3i having an input capacitance 3c, as illustrated in FIG. 14, for example. In response to an input of the reset signal CRST, reset transistors 3f, 3g, and 3h cause short circuits between the gates and drains of the differential transistors 3d and 3e and between the input and output of the INV amplifier 3i, and thereby, the comparator 66x is reset to a balanced state.
In a period from time T31 to time T32, the control circuit 640 drives a comparator output initialization control signal Sr. Then, the ramp-signal generator circuit 630 changes the reference signal Vr from the initial voltage VI to a comparator initialization voltage VR, and holds the comparator initialization voltage VR. Here, the comparator initialization voltage VR is a voltage that is used for compensating for a voltage difference (i.e., comparison) between the reference signal Vr and the pixel signal Vsx after initialization of the comparator 66x, and is higher, by a compensation voltage, than the initial voltage VI previously set by the control circuit 640. In this manner, the comparator 66x (where x=1−p) is defined (initialized) from the balanced state to a state where the comparison result Vcx (where x=1−p) is “H.”
At time T32, the control circuit 640 starts driving a counter clock CK, and the reference signal Vr becomes a sloped ramp signal whose slope starts from the comparator initialization voltage VR. With the start of output of the ramp signal, the counter 67x (where x=1−p) starts down-counting from an initial count value, and comparison for a first AD conversion process starts.
At time T33, when the reference signal Vr in the comparator 66x coincides with the pixel signal Vsx (the reset level voltage V1), the comparison result Vcx transitions to “L” and the counter 67x stops down-counting, and holds the count value (a count width Vd) at this time.
In a period from time T34 to time T35, the control circuit 640 drives the comparator output initialization control signal Sr again. Then, the ramp-signal generator circuit 630 changes the reference signal Vr to the comparator initialization voltage VR again, thereby initializing the comparison result Vcx (where x=1−p) to “H.” The pixel array 610 outputs a pixel signal Vsx which has been changed to a reset level voltage V2, and enters a standby state until the state is stabilized.
At time T35, the control circuit 640 starts driving of the counter clock CK, and the reference signal Vr becomes a sloped ramp signal whose slope starts from the comparator initialization voltage VR. Then, with the start of output of the ramp signal, the counter 67x starts up-counting based on the count value held in the first AD conversion process, and comparison for a second AD conversion process is started.
At time T36, when the reference signal Vr in the comparator 66x coincides with the pixel signal Vsx (the reset level voltage V2), the comparison result Vcx transitions to “L” and the counter 67x stops up-counting, and holds a count value at this time. The difference between the count value at time T33 and the count value at time T36 is equal to the difference value between the first AD conversion process and the second AD conversion process, i.e., serves as an AD conversion result of the difference (V1−V2) in amplitude of the pixel signal Vsx.
In recent years, the number of pixels in a digital camera system has increased rapidly. In addition, a newly installed function of capturing a high-definition video image has increased the speed of driving image sensors. The increased speed causes problems, which will be described below, in AD conversion using the above-described digital CDS, and various techniques have been proposed to solve the problems.
For example, to catch up with the increase in speed, a double-data-rate (DDR) technique that uses timings at both rising and falling edges of a clock is employed. In the above example (Japanese Patent Publication No. 2006-340044), a clock signal line supplies a common clock to the ramp-signal generator circuit 630 and the counters 670. Thus, the clock signal line is extended to a long distance. When the frequency of this clock increases, a load due to wiring resistance and/or wiring capacitance causes rounding of a clock waveform and a decrease in duty ratio, resulting in degradation of differential non-linearity (DNL) characteristics of AD conversion.
To solve such a problem, Japanese Patent Publication No. 2009-077172 proposes a technique for smoothing a ramp signal waveform by dividing, and thereby, reducing the frequency of a clock to be supplied to a ramp-signal generator circuit, and inserting a low-pass filter (LPF) in a path for an output signal from the ramp-signal generator circuit. This technique can reduce degradation of DNL characteristics due to rounding of a clock waveform or a decrease in duty ratio.
As described above, AD conversion of digital CDS is implemented by two AD conversion processes. To achieve high-speed driving, an AD conversion period is preferably minimized.
In view of this, United States Patent Application No. 2010/0271248 proposes a technique for reducing an AD conversion period in digital CDS. Specifically, in this technique, a linear period of a ramp wave is extended within a ramp wave generation period (e.g., a down-counting period or an up-counting period in FIG. 13). More specifically, an output section of the ramp-signal generator circuit is driven by a buffer, and is coupled to a large number of ADCs. An input section of the buffer in the output section of the ramp-signal generator circuit includes an LPF for smoothing glitch noise. Switching of a time constant of this glitch smoothing LPF can reduce rounding at a start of output of a ramp wave.
Japanese Patent Publication No. 2006-337139 shows a technique for enhancing high-speed responsiveness of a ramp wave generator. Specifically, in this technique, a ramp wave and a square wave are added at the same timing, thereby achieving high-speed ramp wave generation.